Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

ABSTRACT

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

TECHNICAL FIELD

The present invention relates to a split gate NAND flash memory structure and more particularly to a bi-directional split gate NAND flash memory structure having only a source and drain at the ends of the NAND flash memory structure.

BACKGROUND OF THE INVENTION

Non-volatile memory integrated circuit chips are well known in the art. See for example U.S. Pat. Nos. 5,029,130 and 6,151,248. One form of a non-volatile memory integrated circuit chip is a “NAND” flash memory device in which a string of serially connected non-volatile memory cells are grouped in a NAND flash memory structure.

Referring to FIG. 1A there is shown a cross-sectional view of a prior art split gate NAND flash memory structure 10. (See “Split-Gate NAND Flash Memory At 120 nm Technology Node Featuring Fast Programming and Erase” by C. Y. Shu et al, 2004 symposium on VLSI Technology Digest of Technical Papers, p. 78–79). The NAND flash memory structure 10 is formed on a semiconductor substrate 12 of a first conductivity type. The NAND flash memory structure 10 has a first region 14 of a second conductivity type and a second region 16 of the second conductivity type in the substrate 12. The first region 14 and the second region 16 are spaced apart from one another to define a continuous channel region between the first region 14 and the second region 16. A plurality of floating gates (18A . . . 18N) are spaced apart from one another with each floating gate 18 positioned over a separate portion of the channel region and separated and insulated therefrom. The structure 10 further has a select gate 20 associated with each floating gate 18. The select gate 20 is positioned over another portion of the channel region, and is immediately adjacent to the associated floating gate 18 and is insulated therefrom. Finally, the structure 10 has a plurality of control gates 22 with each control gate 22 associated with a floating gate 18 and forming a stacked gate configuration with the associated floating gate 18.

Typically, the NAND gate structure 10 is formed in a column direction with the select gate 20 and the control gate 22 connecting the respective select gates and control gates in a row direction. A plan view of an array of such NAND structures 10 is shown in FIG. 1B.

The problem with the NAND structure 10 of the prior art is that it requires two row lines for each cell: one for the select gate 20 and one for the control gate 22. With two lines for each cell and where for non-volatile memory cells the lines must carry high voltages, there would be too many high voltage control lines required for the pitch of each cell. In addition, the NAND structure 10 is uni-directional in operation.

Memory arrays in which the adjacent rows/columns are electrically connected at ends of the array are well known. See, e.g. U.S. Pat. No. 6,825,084 (FIG. 2). Finally, control gates that are substantially T shaped positioned between a pair of floating gates and having a portion over a channel region, and capacitively coupled to the pair of floating gates is also well known in the art. See e.g. U.S. Pat. No. 6,151,248.

Accordingly, there is a need to reduce the line count per cell to thereby improve the pitch of the nonvolatile memory device.

SUMMARY OF THE INVENTION

Accordingly, in the present invention, a NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate and a second region of the second conductivity type in the substrate, spaced apart from the first region. Thus, a channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each insulated from the channel region. A plurality of control gates are spaced apart from one another with each insulated from the channel region. Each control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another with each insulated from the channel region. Each select gate is between a pair of floating gates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view of a NAND flash memory structure of the prior art.

FIG. 1B is a top view of a NAND flash memory device using a plurality of NAND flash memory structures of the prior art shown in FIG. 1A showing the interconnection of one NAND flash memory structure to an adjacent NAND flash memory structure.

FIG. 2 is a schematic cross-sectional view of one embodiment of a NAND flash memory structure of the present invention.

FIG. 3 is a top view of a NAND array using a plurality of NAND flash memory structures of the type shown in FIG. 2.

FIG. 4 is a schematic circuit diagram view of the NAND array shown in FIG. 3.

FIG. 5 is a cross-sectional view of a portion of the NAND flash memory structure of the present invention shown in FIG. 2.

FIGS. 6A–6E show the steps in making the portion of the NAND flash memory structure of the present invention shown in FIG. 5.

FIG. 7 is a schematic cross-sectional view of a variation of the NAND flash memory structure of the present invention shown in FIG. 2.

FIG. 8 is a schematic cross-sectional view of another embodiment of a NAND flash memory structure of the present invention, which is another variation of the embodiment shown in FIG. 2.

FIG. 9 is a schematic cross-sectional view of an embodiment of a NAND flash memory structure similar to the NAND flash memory structure shown in FIGS. 7 and 8.

FIG. 10 is a schematic cross-sectional view of yet another embodiment of a NAND flash memory structure of the present invention.

FIG. 11 is a schematic cross-sectional view of a variation of the embodiment of the NAND flash memory structure of the present invention shown in FIG. 10.

FIG. 12 is a schematic cross-sectional view of a variation of the embodiment of the NAND flash memory structure of the present invention shown in FIG. 10.

FIG. 13 is a schematic cross-sectional view of a variation of the embodiment of the NAND flash memory structure of the present invention shown in FIGS. 11 and 12.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 2 there is shown a cross-sectional view of a first embodiment 30 of a NAND flash memory structure 30 of the present invention. The NAND flash memory structure 30 shown in FIG. 2 is formed on a semiconductor substrate 12 of a first conductivity type, such as P-type. The structure 30 has a first region 14 of a second conductivity type, such as N type, as a source, in the substrate 12. Spaced apart from the first region 14 or the source 14 is a second region 16, such as a drain, also of the second conductivity type, in the substrate 12. As used herein, the term “source” and “drain” may be used interchangeably. As will be disclosed hereinafter, the operation of the NAND flash memory structure 30 of the present invention can be operated with the source 14 and the drain 16 interchanged, i.e. the structure 30 can operate bi-directionally. The first region 14 and the second region 16 are spaced apart from one another to define a continuous channel region 32 there between. A plurality of floating gates 18 are spaced apart from one another and are positioned above the channel region 32 and is insulated therefrom. Each floating gate 18 is positioned over a separate portion of the channel region 32 and controls the conduction of the current in the channel region portion over which the floating gate 18 is positioned. The NAND flash memory structure 30 also comprises a plurality of controls gates 34. Each control gate 34 is associated with and is positioned between a pair of floating gates 18. Each control gate 34 has two portions: a first portion 36 which is over a portion of the channel region 32 adjacent to the associated floating gates 18 and a second portion 38 over the associated floating gates 18 and insulated therefrom and is capacitively coupled to the floating gates 18. The control gate 34 can be a unitary structure as shown in FIG. 2 or the two portions 36 and 38 can be separate portions but electrically connected ex situ, i.e. electrically outside of the NAND flash memory structure 30. In the embodiment shown in FIG. 2, the NAND flash memory structure 30 also comprises a first select gate 40 positioned over a portion of the channel region 32 and insulated therefrom. Each first select gate 40 is associated with and is positioned between a pair of floating gates 18. Thus, each floating gate 18 has an associated control gate 34 to one side and an associated select gate 40 to another side. Each select gate 40 is substantially rectilinearly shaped. The select gate 40 functions as a gate of a conventional MOS transistor. Finally, the NAND flash memory structure 30 also has two second select gates 42, with each positioned over a portion of the channel region 32 and insulated therefrom, and immediately adjacent to the source region 14 and the drain region 16, respectively. Each of the second select gates 42 is substantially “L” shaped.

ARRAY OF NAND FLASH MEMORY STRUCTURES

Referring to FIG. 3 there is shown a top view of an array 50 of NAND flash memory structures 30. The array 50 comprises a plurality of NAND flash memory structures 30 arranged in a plurality of rows and columns. As is well known to those in the art, the term row and column may be used interchangeably. In the embodiment shown in FIG. 3, each NAND flash memory structure 30 is arranged in the column direction, with the source region 14 at one end and the drain region 16 at another end. Further, each NAND flash memory structure 30 in a column shares a common drain region 16 with another NAND flash memory structure at one end and shares a common source region 14 at another end. Finally, as can be seen from FIG. 3, NAND Flash memory structures that are adjacent to one another in the row direction also share a common source region 14. Thus, the NAND structure 30 a has a source region 14 a and a drain region 16 a. The NAND structure 30 b, which is immediately adjacent to the structure 30 a in a row direction shares the common drain region 16 a, and has a source region 14 c. The source region 14 c, however, is also shared with an adjacent structure 30 c, in the row direction. Finally, the first select gates 40 and the second select gates 42 and the control gates 34 are laid out in the row direction.

A schematic circuit diagram of the array 50 is shown in FIG. 4. Each first select gate 40 and second select gate 42 acts as a conventional gate of an MOS transistor, in that a voltage applied to that gate can turn on the portion of the channel region underneath the gate. Each control gate 34 acts as a control gate of a stack floating gate transistor. The voltage applied to the control gate, if sufficient to overcome the charges stored on the associated floating gate, can turn on the portion of the channel region underneath the floating gate.

METHOD OF MANUFACTURING

Referring to FIG. 5, there is shown a cross-sectional view of a portion of the NAND flash memory structure 30 of the present invention. The structure 30 comprises a silicon substrate 12, which typically is of P type. However, as it is well known to those skilled in the arty, that the substrate may also be N type. The portion of the structure 30 also comprises a floating gate oxide layer 60 on the substrate 12. A pair of floating gates 18 are on the oxide layer 60. Between the pair of floating gates 18 is the first portion 36 of the control gate 34. The first portion 36 of the control gate 34 is also insulated from the substrate 12. Each of the two second portions 38 of the control gate 34 extends over the pair of floating gates 18 and is capacitively coupled thereto. The select gate 40 is between a pair of floating gates 18.

The portion of the NAND flash memory structure 30 shown in FIG. 5 can be made by the following process steps. Referring to FIG. 6A there is shown a single crystalline silicon substrate 12, on which is grown a layer of silicon dioxide 70. The layer of silicon dioxide is approximately ninety (90) angstroms in thickness. As will be apparent to those skilled in the art, the dimensions described herein are for a certain geometry size of the NAND structure 30. In the present case, the description is for a device having one hundred thirty (130) mm feature size. The layer of silicon dioxide 70 can be grown by thermal oxidation of silicon or it can be a deposited dielectric. A layer of polysilicon 72 of approximately five hundred (500) angstroms is then deposited on the layer of silicon dioxide 70. The layer of polysilicon 72 can be deposited by low pressure chemical vapor deposition (LPCVD). The polysilicon 72 is then subjected to a high temperature oxidation (HTO) treatment, in which a layer of silicon dioxide 74 is deposited. Approximately one hundred fifty (150) angstroms of silicon dioxide 74 is deposited. Finally, a layer of silicon nitride 76 of approximately two thousand (2000) angstroms in thickness is then deposited on the layer of silicon dioxide 74. The layer of silicon nitride 76 can be deposited by LPCVD. The resultant structure is shown in FIG. 6A.

The structure shown in FIG. 6A is then subject to a photomasking operation in which select portions of the silicon nitride layer 76 is covered by photoresist and then exposed by an appropriate mask. The mask is removed, with the unexposed photoresist removed. The structure is then subjected to a silicon nitride RIE etch removing the silicon nitride 76 that is not covered by the photoresist. The etch continues until it reaches the layer 74 of silicon dioxide. The photoresist that remains covering the silicon nitride 76 is then removed. A layer of silicon dioxide 78 (TEOS) is then deposited on the structure. The layer 78 of TEOS is approximately one thousand (1000) angstroms thick. The structure is then subjected to a RIE TEOS etch, stopping at the polysilicon layer 72. The resultant operation forms TEOS spacers 78 which abut the unexposed strips of silicon nitride 76. The resultant structure is shown in FIG. 6B.

The structure shown in FIG. 6B is then subjected to an RIE polysilicon etch process. The RIE polysilicon etch removes the exposed portion of the polysilicon layer 72, exposing the underlying silicon dioxide layer 70. The structure is then dipped in HF acid to remove the TEOS oxide spacer 78 and the portion of the silicon dioxide layer 74 beneath the TEOS oxide spacer 78. A layer 80 of HTO is then deposited everywhere. The resultant structure is shown in FIG. 6C.

Polysilicon 82 is then deposited everywhere in the structure shown in FIG. 6C. In particular, polysilicon 82 is deposited in the regions between adjacent strips of silicon nitride 76, covered by the HTO oxide 80. The structure is then planarized and polished using CMP, removing the HTO oxide 80 on the silicon nitride 76, until the silicon nitride 76 is exposed and is planar with the exposed surface of the deposited polysilicon 82. The structure is then oxidized. Since the only exposed polysilicon is that region of the polysilicon 82 which is exposed, oxide 84 is formed on the polysilicon 82. The structure is then dipped in HF acid. The resultant structure is shown in FIG. 6D.

The structure shown in FIG. 6D is dipped in hot phosphoric acid which removes the exposed silicon nitride 76. The structure is then subjected to an RIE oxide etch removing the exposed portion of the layer 74 of silicon dioxide. The structure is then subjected to a RIE polysilicon etch removing exposed portions of the polysilicon 72, leaving two separate portions of polysilicon 72, which will be the pair of floating gates that are adjacent to the first select gate. The structure is then subjected to an RIE oxide etch removing the exposed portions of the silicon dioxide layer 70, reaching the substrate 12. An oxide layer 86 is grown or deposited on the exposed silicon substrate 12. The silicon dioxide layer 86 forms the gate oxide layer for the first select gates. Thus the thickness of the gate oxide 86 for the first select gate 40 can be different from the gate oxide 70 for the floating gate 72. Finally, polysilicon 88 is deposited forming the first select gate 40. The structure is then subjected to a poly etchback operation. The resultant structure is shown in FIG. 6E.

METHODS OF OPERATION

Erase Operation No. 1

In a first method of erasing a NAND flash memory structure 30 of the present invention, floating gates 18 that are in the same row are erased at the same time. This is accomplished as follows. Let us assume that the floating gate 18 c and those floating gates in the same row are to be erased simultaneously. Then the following voltages are applied. The source region 14 and the drain region 16 are all held at ground. The second select gates 42 are also held at ground. A positive voltage, such as plus eight volts (+8v) is applied to the first select gate 40 a which is immediately adjacent to the selected floating gate 18 c, while all of the other first select gates 40 are held at ground. Finally, a ground or negative voltage, such as negative ten volts (−10v), is applied to the control gate 34 b which is immediately adjacent to the selected floating gate 18 c, on the other side of the first select gate 40 a, while ground voltage is applied to all of the other control gates 34. The result is that the negative voltage from the control gate 34 b will repel the electrons on the floating gate 18 c, while the positive voltage on the first select gate 40 a will attract the electrons stored on the floating gate 18 c. The electrons will tunnel through the mechanism of Fowler-Nordheim from the floating gate 18 c to the first select gate 40 a. Because each of the first select gates 40 a and the control gate 34 b extend in the row direction, all of the floating gates 18 c in the same row will be erased at the same time.

In a variation of the foregoing method, if a negative voltage, such as negative ten volts (−10v) were applied to the control gate 34 a, which is on the other side of the floating gate 18 b, which is adjacent to the first select gate 40 a, then all of the floating gates in the same row as the floating gates 18 b will also be erased. Thus, in this variation, two rows of floating gates (18 a and 18 b) can be erased simultaneously.

Erase Option No. 2

In this method of erasing a NAND structure 30, The source region 14 and the drain region 16 are all held at ground. The second select gates 42 are also held at ground. All of the first select gates 40 are held at ground. A negative voltage, such as negative ten volts (−10v), is applied to the control gates 34 in each NAND structure 30. A positive voltage, such as plus ten volts (+10v) is applied to the substrate 12. All of then floating gates 18 in the NAND structure are erased at the same time. In this mode of operation, however, the structure has to be of triple well construction so that different wells can be formed in the substrate 12 so that only portions of the array 50 is erased at the same time. For example, if the NAND structures 30 (30 a–30 p) shown in FIG. 3 on the left side were made in one triple well, and the NAND structures 30 (30 q–30 af) shown in FIG. 3 on the right side were made in another triple well, then one can erase simultaneously all of the floating gates 18 in the NAND structures (30 a–30 p) by applying a positive voltage to that well, while keeping the voltage to the well for the NAND structures (30 q–30 af) at ground. In this manner of erase, the electrons from the floating gates 18 are tunneled through the gate oxide 70 into the substrate 12 (or the well of the substrate 12).

Programming

The basic mechanism of programming for the NAND flash memory structure 30 of the present invention is by the mechanism of source side hot electron injection or mid-channel hot electron injection. Assume now that the floating gate 18 c is to be programmed. Then the voltages applied are as follows. The source region 14 is held at ground. A positive voltage, such as +4.5 volts is applied to the drain region 16. A positive voltage, such as +6 volts is applied to the second gates 42 a and 42 b, so that the channel regions beneath those second select gates are turned on. The control gate 34 b, which is immediately adjacent to the selected floating gate 18 c is applied with a voltage of 7–11 volts, while all of the rest of the control gates is applied with +10 volts. The +10 volts applied to all the other control gates, such as 34 a, 34 c, 34 d etc., is sufficient to cause the channel region underneath the floating gates to which these control gates are capacitively coupled to turn on, irrespective of whether these floating gates are charged or not. The first select gate 40 a which is immediately adjacent to the selected floating gate 18 c is applied with a positive voltage of +1.5 volts, while all of the other first select gates 40 are applied with +6 volts. The application of +1.5 volts turns on weakly the channel region beneath that first select gate 40 a, while the application of +6 volts to all the other first select gates 40 strongly turns on the channel region beneath those first select gates 40. As a result, programming of the selected floating gate 18 c occurs in the following manner.

Electrons are attracted from the source region 14 to the drain region 126, since all of the regions of the channel 32 are turned on. As the electrons approach the portion of the channel region 32 beneath the first select gate 40 a, that portion of the channel region is weakly turned on. However, because of the strong capacitive coupling between the floating gate 18 c and the control gate 34 b, and the large voltage applied to the control gate 34 b, the electrons in the channel region 32 beneath the select gate 40 a “sees” a strong positive voltage on the selected floating gate 18 c. Thus, electrons are accelerated to the floating gate 18 c, and are injected across the gate oxide region 60, thereby programming the selected floating gate 18 c.

As can be seen by FIG. 3, adjacent NAND flash memory structures 30 in the row direction share a common source region 14 to one side and a common drain region 16 to another side. To minimize programming disturbance on adjacent NAND flash memory structures 30, the voltages applied to the other source regions 14 and drain regions 16 as follows. Let us assume that the selected floating gate 18 c is from the selected NAND flash memory structure 30 c. Then the voltages applied are: ground voltage applied to source region 14 c, +4.5 volts applied to the drain region 16 c, and 2.5 volts applied to source region 14 e. The application of +2.5 volts to the source region 14 e, minimizes the programming disturbance to the NAND flash memory structure 30 d. Finally, all of the other source regions 14 and drain regions 16 are held at ground.

The NAND flash memory structure 30 is bi-directional. Thus, programming can also occur in a direction opposite to that shown and described above, to program, for example, the floating gate 18 d. To program the floating gate 18 d, the following voltages are applied: The drain region 16 is held at ground. A positive voltage, such as +4.5 volts is applied to the source region 14. A positive voltage, such as +6 volts is applied to the second gates 42 a and 42 b, so that the channel regions beneath those second select gates are turned on. The control gate 34 b, which is immediately adjacent to the selected floating gate 18 d is applied with a voltage of 7–11 volts, while all of the rest of the control gates is applied with +10 volts. The +10 volts applied to all the other control gates, such as 34 a, 34 c, 34 d etc., is sufficient to cause the channel region underneath the floating gates to which these control gates are capacitively coupled to turn on, irrespective of whether these floating gates are charged or not. The first select gate 40 b which is immediately adjacent to the selected floating gate 18 d is applied with a positive voltage of +1.5 volts, while all of the other first select gates 40 are applied with +6 volts. The application of +1.5 volts turns on weakly the channel region beneath that first select gate 40 b, while the application of +6 volts to all the other first select gates 40 strongly turns on the channel region beneath those first select gates 40. The action of mid-channel hot electron injection, which is same as that described before, will then occur, causing electrons from the drain region 16 to be injected onto the floating gate 18 d.

Read Operation

Read Option No. 1

The first option to read a selected floating gate is through the mechanism of voltage sensing. Assume now that it is desired to read floating gate 18 c. The voltages applied are as follows: A positive voltage such as +1.5 volts is applied to the drain region 16. The voltage at the source 14 is sensed under a load of −100 nanoamperes. A positive voltage of +4 volts is applied to the second select gates 42 a and 42 b. A positive voltage of, for example +1.5 volts, is applied to the control gate 34 b, which is immediately adjacent to the selected floating gate 18 c, while a positive voltage of +4.0 volts is applied to all of the other control gates 34. The voltage of +4 volts is sufficient to turn on the portion of the channel region 32 underneath the floating gates 18 with which the control gates 34 are associated, irrespective of the state of charge of the floating gates 18. The voltage of +1.5 volts is sufficient to turn on the portion of the channel region 32 underneath the selected floating gate 18 c in the event the selected floating gate 18 c is not programmed. However, if the selected floating gate 18 c is programmed, the voltage of +1.5 volts is insufficient o turn on the portion of the channel region 32 underneath the selected floating gate 18 c or turns it on very weakly. A large positive voltage, such as +7 volts is applied to the first select gate 40 b which is immediately adjacent to the floating gate 18 d which along with the selected floating gate 18 c is capacitively coupled to the control gate 34 b. The large positive voltage on the first select gate 40 b is sufficient to cause the portion of the channel region underneath the floating gate 18 d to turn on, even if the floating gate 18 d is programmed. All of the other first select gates 40 are supplied with a voltage of +1.5 volts which is sufficient to turn on the portion of the channel region 32 underneath those first select gates 40.

In operation, the voltage at the source region 14 is sensed. The voltage is dependent upon whether the selected floating gate 18 c is programmed or not.

To minimize read disturbance on adjacent NAND flash memory structures 30, the voltages are as follows. Assume that the selected NAND structure is structure 30 c. Then the voltage applied are: voltage sensing occurs at source region 14 c, +1.5 volts is applied at drain region 16 c, 0 volts is applied to all other drain regions 16, the source region 14 e is held floating, and all other source regions 14 are applied with ground voltage.

The NAND flash memory structure 30 is capable of being read bi-directionally. Thus to read the floating gate 18 d, the voltages applied are as follows: A positive voltage such as +1.5 volts is applied to the source region 14. The voltage at the drain region 16 is sensed under a load of −100 nanoamperes. A positive voltage of +4 volts is applied to the second select gates 42 a and 42 b. A positive voltage of, for example +1.5 volts, is applied to the control gate 34 b, which is immediately adjacent to the selected floating gate 18 d, while a positive voltage of +4.0 volts is applied to all of the other control gates 34. The voltage of +4 volts is sufficient to turn on the portion of the channel region 32 underneath the floating gates 18 with which the control gates 34 are associated, irrespective of the state of charge of the floating gates 18. The voltage of +1.5 volts is sufficient to turn on the portion of the channel region 32 underneath the selected floating gate 18 d in the event the selected floating gate 18 d is not programmed. However, if the selected floating gate 18 d is programmed, the voltage of +1.5 volts is insufficient o turn on the portion of the channel region 32 underneath the selected floating gate 18 d or turns it on very weakly. A large positive voltage, such as +7 volts is applied to the first select gate 40 a which is immediately adjacent to the floating gate 18 c which along with the selected floating gate 18 c is capacitively coupled to the control gate 34 b. The large positive voltage on the first select gate 40 a is sufficient to cause the portion of the channel region underneath the floating gate 18 c to turn on, even if the floating gate 18 c is programmed. All of the other first select gates 40 are supplied with a voltage of +1.5 volts which is sufficient to turn on the portion of the channel region 32 underneath those first select gates 40.

Read Option No. 2

The second option to read a selected floating gate is through the mechanism of current sensing. Assume now that it is desired to read floating gate 18 c. The voltages applied are as follows: A positive voltage such as +1.0 volts is applied to the drain region 16, and zero volts at the source region 14. The current flowing at the drain region 16 is sensed. A positive voltage of +3 volts is applied to the second select gates 42 a and 42 b. A positive voltage of, for example +1.5 volts, is applied to the control gate 34 b, which is immediately adjacent to the selected floating gate 18 c, while a positive voltage of +4.0 volts is applied to all of the other control gates 34. The voltage of +4 volts is sufficient to turn on the portion of the channel region 32 underneath the floating gates 18 with which the control gates 34 are associated, irrespective of the state of charge of the floating gates 18. The voltage of +1.5 volts is sufficient to turn on the portion of the channel region 32 underneath the selected floating gate 18 c in the event the selected floating gate 18 c is not programmed. However, if the selected floating gate 18 c is programmed, the voltage of +1.5 volts is insufficient o turn on the portion of the channel region 32 underneath the selected floating gate 18 c or turns it on very weakly. A large positive voltage, such as +5 volts is applied to the first select gate 40 b which is immediately adjacent to the floating gate 18 d which along with the selected floating gate 18 c is capacitively coupled to the control gate 34 b. The large positive voltage on the first select gate 40 b is sufficient to cause the portion of the channel region 32 underneath the floating gate 18 d to turn on, even if the floating gate 18 d is programmed. All of the other first select gates 40 are supplied with a voltage of +1.5 volts which is sufficient to turn on the portion of the channel region 32 underneath those first select gates 40.

In operation, the current at the drain region 16 is sensed. The current is dependent upon whether the selected floating gate 18 c is programmed or not.

To minimize read disturbance on adjacent NAND flash memory structures 30, the voltages are as follows. Assume that the selected NAND structure is structure 30 c. Then the voltage applied are: +1.0 volts is applied at drain region 16 c, 0 volts is applied to all other drain regions 16, the source region 14 c is held at ground, while the source region 14 e is supplied with +1.5 volts. Thus, no current flows in the NAND structure 30 d. All other source regions 14 are applied with ground voltage.

The NAND flash memory structure 30 is capable of being read bi-directionally. Thus to read the floating gate 18 d, the voltages applied are as follows: A positive voltage such as +1.0 volts is applied to the source region 14, and zero volts at the drain region 16. The current flowing at the source region 14 is sensed. A positive voltage of +3 volts is applied to the second select gates 42 a and 42 b. A positive voltage of, for example +1.5 volts, is applied to the control gate 34 b, which is immediately adjacent to the selected floating gate 18 d, while a positive voltage of +4.0 volts is applied to all of the other control gates 34. The voltage of +4 volts is sufficient to turn on the portion of the channel region 32 underneath the floating gates 18 with which the control gates 34 are associated, irrespective of the state of charge of the floating gates 18. The voltage of +1.5 volts is sufficient to turn on the portion of the channel region 32 underneath the selected floating gate 18 d in the event the selected floating gate 18 c is not programmed. However, if the selected floating gate 18 d is programmed, the voltage of +1.5 volts is insufficient o turn on the portion of the channel region 32 underneath the selected floating gate 18 c or turns it on very weakly. A large positive voltage, such as +5 volts is applied to the first select gate 40 a which is immediately adjacent to the floating gate 18 c which along with the selected floating gate 18 d is capacitively coupled to the control gate 34 b. The large positive voltage on the first select gate 40 a is sufficient to cause the portion of the channel region 32 underneath the floating gate 18 c to turn on, even if the floating gate 18 c is programmed. All of the other first select gates 40 are supplied with a voltage of +1.5 volts which is sufficient to turn on the portion of the channel region 32 underneath those first select gates 40.

OTHER EMBODIMENTS OF THE NAND STRUCTURE

Referring to FIG. 7, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 130 of the present invention. The structure 130 is similar to the structure 30 shown and described in FIG. 2. The only difference between the structure 130 and the structure 30 is that with the structure 130, additional second regions 90(a–n) are in the channel region 32 between the source region 14 and the drain region 16. Each of these additional regions 90(a–n) is underneath a the first portion 36 of the control gate 34. The control gate 34 however remains insulated from the substrate 12, and the channel region 32. With the addition of these second regions 90, the flow of the electrons in the channel region 32 between the source region 14 and the drain region 16 can be more finely controlled. These regions can extend in the row direction parallel to the control gate 34 and the first select gates 40.

Referring to FIG. 8, there is shown a cross sectional view of yet another embodiment of a NAND flash memory structure 230 of the present invention. The structure 230 is similar to the structure 30 shown and described in FIG. 2. The only difference between the structure 230 and the structure 30 is that in the structure 230, the second control gates 42, immediately adjacent to the source region 14 and the drain region 16, are also rectilinearly shaped, similar to the first control gates 40.

Referring to FIG. 9, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 330 of the present invention. The structure 330 is similar to the structures 30/130/230 shown and described in FIGS. 2/7/8. Similar to the structure 130 shown and described in FIG. 7, the structure 330 has a plurality of second regions 90(a–n) between the source region 14 and the drain region 16. Further, similar to the structure 230 shown and described in FIG. 8, the structure 330 has second select gates 42 that are substantially rectilinearly shaped.

Referring to FIG. 10, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 430 of the present invention. The structure 430 is similar to the structure 230 shown and described in FIG. 8. The only difference between the structure 430 and the structure 430 is that the floating gates 18 and the associated control gate 34 are in a trench. In contrast, in the structure 230, all of the control gates, first and second select gates, and floating gates are on the planar surface of the silicon substrate.

Referring to FIG. 11, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 530 of the present invention. The structure 530 is similar to the structures 430 shown and described in FIG. 10, and the structure 130 shown in FIG. 7. The structure 530, similar to the structure 430, has the floating gates 18 and the associated control gates 34 in trenches. In addition, the structure 530 has a plurality of second regions 90, with each region 90 being along the bottom of each trench, similar to the second region 90 being along the bottom of the first portion 36 of the control gate 34, shown and described in FIG. 7.

Referring to FIG. 12, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 630 of the present invention. The structure 630 is similar to the structures 430 shown and described in FIG. 10. The only difference is that in the structure 630, the second select gates 42 are “L” shaped, whereas the second select gates 42 in the structure 430 shown in FIG. 10 are rectilinearly shaped.

Referring to FIG. 13, there is shown a cross sectional view of another embodiment of a NAND flash memory structure 730 of the present invention. The structure 730 is similar to the structures 630 shown and described in FIG. 12, and the structure 530 shown and described in FIG. 11. The only difference between the structure 730 and the structure 630 is the addition of a plurality of second regions 90 at the bottom wall of each trench, similar to the structure 530.

As can be seen from the foregoing, a bi-directional high density NAND flash memory structure and array comprising of split gate memory cells is disclosed. 

1. A NAND flash memory structure formed on a semiconductor substrate of a first conductivity type, said structure comprising: a first region of a second conductivity type in said substrate; a second region of the second conductivity type in said substrate, spaced apart from said first region, thereby defining a channel region therebetween; a plurality of floating gates, spaced apart from one another, each insulated from the channel region; a plurality of control gates, spaced apart from one another, each insulated from the channel region, each control gate being between a pair of floating gates and being capacitively coupled to said pair of floating gates; and a plurality of select gates, spaced apart from one another, each insulated from the channel region, each select gate being between a pair of floating gates.
 2. The NAND structure of claim 1 wherein each floating gate is between a control gate and a select gate.
 3. The NAND structure of claim 1 wherein each floating gate is in a trench in said substrate and is spaced apart from a sidewall of the trench.
 4. The NAND structure of claim 3 wherein each control gate is in a trench capacitively coupled to a pair of floating gates in the trench and is substantially T shaped.
 5. The NAND structure of claim 1 wherein a first select gate is insulated from said channel region and is immediately adjacent to said first region; and wherein a second select gate is insulated from said channel region and is immediately adjacent to said second region.
 6. The NAND structure of claim 5 wherein each of said first select gate and said second select gate is substantially rectilinearly shaped.
 7. The NAND structure of claim 5 wherein each of said first select gate and said second select gate is substantially “L” shaped.
 8. The NAND structure of claim 1 further comprising: a plurality of third regions of the second conductivity type in said substrate, each capacitively coupled to said control gate.
 9. The NAND structure of claim 1 wherein said channel region between said first region and said second region is a continuous channel region therebetween and each control gate is substantially T shaped.
 10. An array of NAND flash memory structures, said array comprising: a semiconductor substrate of a first conductivity type; a plurality of NAND structure, each structure comprising: a first region of a second conductivity type in said substrate; a second region of the second conductivity type in said substrate, spaced apart from said first region, in a first direction, thereby defining a channel region therebetween; a plurality of floating gates, spaced apart from one another, each insulated from the channel region; a plurality of control gates, spaced apart from one another, each insulated from the channel region, each control gate being between a pair of floating gates and being capacitively coupled to said pair of floating gates; a plurality of select gates, spaced apart from one another, each insulated from the channel region, each select gate being between a pair of floating gates; and wherein NAND structures adjacent to one another in a second direction, substantially perpendicular to the first direction have the select gate connected to one another in the second direction, and the control gate connected to one another in the second direction.
 11. The array of claim 10 further comprising: a plurality of active regions in continuous strips parallel to one another in the first direction with an isolation region separating each pair of adjacent active regions; wherein each of the select gate connecting one NAND structure to an adjacent NAND structure in the second direction crosses an isolation region; and wherein each of the control gate connecting one NAND structure to an adjacent NAND structure in the second direction crosses an isolation region.
 12. The array of claim 11 wherein the first region of a first NAND structure is electrically connected to the first region of a second NAND structure adjacent to one side of the first NAND structure in the first direction; and wherein the second region of the first NAND structure is electrically connected to the second region of a third NAND structure adjacent to another side of the first NAND structure in the first direction.
 13. The array of claim 10 wherein each floating gate is between a control gate and a select gate.
 14. The array of claim 10 wherein each floating gate is in a trench in said substrate and is spaced apart from a sidewall of the trench.
 15. The array of claim 14 wherein each control gate is in a trench capacitively coupled to a pair of floating gates in the trench and is substantially T shaped.
 16. The array of claim 10 further comprising: a plurality of third regions of the second conductivity type in said substrate, each capacitively coupled to said control gate.
 17. The array of claim 10 wherein said channel region between said first region and said second region is a continuous channel region therebetween and each control gate is substantially T shaped.
 18. The array of claim 10 wherein NAND structures connected electrically to one another in series and co-linear to one another terminate at a first end and at a second end, with said first end addressed by a first address, and the second end addressed by a second address, different from the first address. 